This work proposes a structural enhancement and a new technique to design the loop filter (LF) of a third-order phase-locked loop (PLL) to enhance the PLL dynamic performance under abnormal grid conditions. The proposed PLL combines a moving average filter (MAF) and an arbitrarily delayed signal cancelation (ADSC) for structural enhancement to achieve DC-offset rejection and harmonics elimination. The window length of the MAF is selected to be one-sixth of the fundamental grid period to remove non-triple odd harmonics and speed up the PLL dynamic response. The triple harmonics are eliminated, adopting the line-to-line voltage concept, while the ADSC operator rejects the DC offset. The LF design is based on a modified third-order polynomial tuned using stochastic optimization to minimize the settling time of the frequency deviation, offering better dynamic performance over the symmetrical optimum method (SOM) and achieving synchronization within one grid cycle. The PLL mathematical model, small-signal model, and LF design based on the modified polynomial are discussed. Finally, the proposed PLL performance is verified numerically and experimentally with comparisons with other PLLs to demonstrate the effectiveness of the proposed work.