Abstract
The DC-link capacitor in power electronic systems is one of the most vulnerable components in terms of reliability. Since a reliable design of the DC-link capacitor depends on an accurate estimation of its current ripple, this paper proposes analytical equations to model the influence of dead-time on the input current ripple of a three-phase voltage source inverter. The effect of dead-time is modeled as a delay in the rising edges of the input current waveform. The proposed analytical equations are derived and then verified by simulations and experiments. The proposed equations generally provide better accuracy in predicting the input current ripple value compared to the benchmark equations. From the simulation and experimental results, the proposed equations are optimized for dead-time values more than 0.7 μs and modulation indices less than or equal to 0.7. Limitations of the proposed equations are also discussed. For small phase displacements and high modulation indices (0.8 to 1), the accuracy decreases because of the influence of AC output current ripple. For small modulation indices (less than 0.2) and a high value of dead-time (2 μs), the accuracy also decreases due to distortion in the phase current waveforms.