LAPSE:2023.4430v1
Published Article
LAPSE:2023.4430v1
Design and Validation of a Reduced Switching Components Step-Up Multilevel Inverter (RSCS-MLI)
February 23, 2023
Abstract
A reduced switching components step-up multilevel inverter (RSCS-MLI) is presented in the paper. The basic circuit of the proposed MLI can produce 11 levels in the output voltage with a reduced number of switching components. The other features of the proposed circuit include a low value of voltage stresses and the inherent generation of the voltage levels pertaining to the negative half without the requirement of an H-bridge. Fundamental frequency switching technique, also known as Nearest Level Control (NLC) technique, is implemented in the proposed topology for generating the switching signals. The experimental total harmonic distortion (THD) in the output voltage comes out to be 9.4% for modulation index equal to 1. Based on different parameters, a comparative study has been shown in the paper, which makes the claim of the proposed MLI stronger. An experimental setup is prepared to carry out the hardware implementation of the proposed structure and monitor its performance under dynamic load conditions, which is also used to verify the simulation results. Power loss analysis, carried out by using PLECS software, helps us to gain insight into different losses occurring while operating the inverter. The different results are explained and analyzed in the paper.
Keywords
multilevel inverter, NLC, RSCS-MLI, total harmonic distortion
Suggested Citation
Wasiq M, Sarwar A, Sarwer Z, Tariq M, Ahmad S, Al-Shayea AM, Hossain J. Design and Validation of a Reduced Switching Components Step-Up Multilevel Inverter (RSCS-MLI). (2023). LAPSE:2023.4430v1
Author Affiliations
Wasiq M: Department of Electric Power Engineering, Budapest University of Technology and Economics, 1111 Budapest, Hungary [ORCID]
Sarwar A: Department of Electrical Engineering, ZHCET, Aligarh Muslim University, Aligarh 202002, India [ORCID]
Sarwer Z: Department of Electrical Engineering, ZHCET, Aligarh Muslim University, Aligarh 202002, India [ORCID]
Tariq M: Department of Electrical Engineering, ZHCET, Aligarh Muslim University, Aligarh 202002, India [ORCID]
Ahmad S: Industrial Engineering Department, College of Engineering, King Saud University, P.O. Box 800, Riyadh 11421, Saudi Arabia
Al-Shayea AM: Industrial Engineering Department, College of Engineering, King Saud University, P.O. Box 800, Riyadh 11421, Saudi Arabia [ORCID]
Hossain J: School of Electrical and Data Engineering, University of Technology Sydney, Sydney 2000, Australia
Journal Name
Processes
Volume
9
Issue
11
First Page
1948
Year
2021
Publication Date
2021-10-29
ISSN
2227-9717
Version Comments
Original Submission
Other Meta
PII: pr9111948, Publication Type: Journal Article
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LAPSE:2023.4430v1
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https://doi.org/10.3390/pr9111948
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