Abstract
A thermal network will be presented to model a multi-layer structure consisting of a semiconductor structure, integrated Peltier heat pump and a cooling fin. A criterion will be set up to determine the optimal Peltier current to minimise the chip temperature using the power dissipation as the control parameter. Compared with classical methods, the proposed solution does not show any time delays in response to power changes and is not sensitive to the position of chip temperature sensors. It does not generate chip temperature oscillations. The idea can be applied in each integrated circuit cooled with Peltier heat pumps, e.g., power devices, high-performance processors, high-frequency integrated circuits, etc. The authors present a simple mathematical formula that can be easily implemented in the software of a processor being cooled. As a consequence, the device is able to operate with maximum efficiency assuming required reliability. Theoretical considerations are illustrated by some results of computations. The paper is addressed to designers involved in the creation of devices dissipating a significant amount of heat energy.