LAPSE:2024.1009v1
Published Article
LAPSE:2024.1009v1
An Optimal Switching Sequence Model Predictive Control Scheme for the 3L-NPC Converter with Output LC Filter
June 7, 2024
In some applications of microgrids and distributed generation, it is necessary to feed islanded or stand-alone loads with high-quality voltage to provide low total harmonic distortion (THD). To fulfil these demands, an LC filter is usuallyconnected to the output terminals of power electronics converters. A cascaded voltage and current control loop with pulse-width modulation schemes are used to regulate the voltages and currents in these systems. However, these strategies have some drawbacks, particularly when multiple-input−multiple-output plants (MIMO) are controlled using single-input−single-output (SISO) design methods. This methodology usually produces a sluggish transient response and cross−coupling between different control loops and state variables. In this paper, a model predictive control (MPC) strategy based on the concept of optimal switching sequences (OSS) is designed to control voltage and current in an LC filter connected to a three-level neutral-point clamped converter. The strategy solves an optimisation problem to achieve control of the LC filter variables, i.e., currents and output voltages. Hardware-in-the-loop (HIL) results are obtained to validate the feasibility of the proposed strategy, using a PLECS−RT HIL platform and a dSPACE Microlab Box controller. In addition to the good dynamic performance of the proposed OSS−MPC, it is demonstrated using HIL results that the control algorithm is capable of obtaining low total harmonic distortion (THD) in the output voltage for different operating conditions.
Keywords
model predictive control (MPC), multilevel inverters, optimal control, optimal switching sequence (OSS)
Suggested Citation
Herrera F, Mora A, Cárdenas R, Díaz M, Rodríguez J, Rivera M. An Optimal Switching Sequence Model Predictive Control Scheme for the 3L-NPC Converter with Output LC Filter. (2024). LAPSE:2024.1009v1
Author Affiliations
Herrera F: Electrical Engineering Department, University of Chile, Avda. Beauchef 851, Santiago 8370451, Chile
Mora A: Electrical Engineering Department, Universidad Técnica Federico Santa María, Valparaíso 2390123, Chile [ORCID]
Cárdenas R: Electrical Engineering Department, University of Chile, Avda. Beauchef 851, Santiago 8370451, Chile [ORCID]
Díaz M: Electrical Engineering Department, University of Santiago of Chile, Santiago 9170125, Chile [ORCID]
Rodríguez J: Engineering Faculty, Universidad San Sebastian, Santiago 4080871, Chile [ORCID]
Rivera M: Power Electronics, Machines and Control (PEMC) Research Group, Department of Electrical and Electronic Engineering, Faculty of Engineering, University of Nottingham, 15 Triumph Rd, Lenton, Nottingham NG7 2GT, UK; Laboratorio de Conversión de Energías y [ORCID]
Journal Name
Processes
Volume
12
Issue
2
First Page
348
Year
2024
Publication Date
2024-02-06
Published Version
ISSN
2227-9717
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Original Submission
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PII: pr12020348, Publication Type: Journal Article
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LAPSE:2024.1009v1
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doi:10.3390/pr12020348
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Jun 7, 2024
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